Zero Delay Buffer; Cmt To Cmt Connection - Xilinx 7 Series User Manual

Chapter 3: Clock Management Tile

Zero Delay Buffer

The MMCM can also be used to generate a zero delay buffer clock. A zero delay buffer can
be useful for applications where there is a single clock signal fan out to multiple
destinations with a low skew between them. This configuration is shown in the
Figure
designed to match the trace to the external components. In this configuration, it is assumed
that the clock edges are aligned at the input of the FPGA and the input of the external
component. The input clock buffers for CLKIN and CLKFBIN must be in the same bank.
X-Ref Target - Figure 3-14
In some cases, precise alignment cannot occur because of the difference in loading between
the input capacitance of the external component and the feedback path capacitance of the
FPGA. For example, the external components can have an input capacitance of 1 pF to 4 pF
while the FPGA has an input capacitance of around 8 pF. There is a difference in the signal
slope, which is basically skew. Designers need to be aware of this effect to ensure timing.

CMT to CMT Connection

The MMCM and PLL can be cascaded using CLKOUT0 to CLKOUT3 through the CMT
backbone to allow generation of a greater range of clock frequencies. No buffer is needed
when used with the CMT backbone
offset between the output clocks of the two MMCMs because the backbone delay is not
compensated.
The frequency range restrictions still apply.
the final output frequency and the input frequency and counter settings of the two
MMCMs
the second MMCM and the input clock is undefined, and an additional phase offset is
added between the two MMCMs because the backbone connection is not compensated. To
cascade MMCMs, route the output of the first MMCM to the CLKIN pin of the second
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90
3-14. Here, the feedback signal drives off chip and the board trace feedback is
IBUFG
Inside FPGA
CLKIN1
CLKFBIN
RST
CLKFBOUT
CLKFBOUTB
MMCM
Figure 3-14: Zero Delay Buffer
(Figure 3-15 and Figure
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BUFG
CLKOUT0
CLKOUT0B
CLKOUT1
CLKOUT1B
CLKOUT2
CLKOUT2B
CLKOUT3B
CLKOUT4
CLKOUT5
BUFG
CLKOUT6
LOCKED
(Figure 3-15 and Figure
Equation 3-12
3-16). The phase relationship between the output clock of
7 Series FPGAs Clocking Resources User Guide
OBUF
To
External
Components
ug472_c2_13_061710
3-16). There will be a phase
shows the relationship between
UG472 (v1.5) July 13, 2012