Xilinx 7 Series User Manual page 104
Fpgas clocking resources
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- User manual (306 pages) ,
- User manual (74 pages) ,
- User manual (58 pages)
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Appendix A: Multi-Region Clocking
X-Ref Target - Figure A-6
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104
Clock Region Boundary
MRCC
RST
Clock Region Boundary
Figure A-6: Driving Multiple BUFRs (With Divide) and BUFIO
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÷
BUFR
BUFIO
÷
BUFR
BUFMRCE
BUFIO
BUFR Alignment
Circuit
÷
BUFR
BUFIO
7 Series FPGAs Clocking Resources User Guide
ISERDES/OSERDES
CLKDIV
CLK
ISERDES/OSERDES
CLKDIV
CLK
ISERDES/OSERDES
CLKDIV
CLK
ug472_aA_06_051311
UG472 (v1.5) July 13, 2012
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