Xilinx 7 Series User Manual page 80

Chapter 3: Clock Management Tile
Table 3-7: MMCM Attributes (Cont'd)
Attribute
CLKOUT[1:6]_DIVIDE
CLKOUT[0]_DIVIDE_F
CLKOUT[0:6]_PHASE
CLKOUT[0:6]_
DUTY_CYCLE
CLKFBOUT_MULT_F
DIVCLK_DIVIDE
CLKFBOUT_PHASE
REF_JITTER1
REF_JITTER2
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Type Allowed Values
Integer 1 to 128
Integer 1 to 128 or
or 2.000 to 128.000 in
Real increments of 0.125
Real –360.000 to 360.000 in
increments of
1/56 the F and/or
VCO
increments depending
on CLKOUT_DIVIDE.
Real 0.01 to 0.99
Integer 2 to 64 or
or 2.000 to 64.000 in
Real increments of 0.125
Integer 1 to 106
Real 0.00 to 360.00
Real 0.000 to 0.999
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Default Description
1 Specifies the amount to divide the
associated CLKOUT clock output
1
if a different frequency is desired.
This number in combination with
the CLKFBOUT_MULT_F and
DIVCLK_DIVIDE values will
determine the output frequency.
0.0 Allows specification of the output
phase relationship of the
associated CLKOUT clock output
in number of degrees offset (i.e., 90
indicates a 90° or ¼ cycle offset
phase offset while 180 indicates a
180° offset or ½ cycle phase offset).
0.50 Specifies the Duty Cycle of the
associated CLKOUT clock output
in percentage (i.e., 0.50 will
generate a 50% duty cycle).
5 Specifies the amount to multiply
all CLKOUT clock outputs if a
different frequency is desired. This
number, in combination with the
associated CLKOUT#_DIVIDE
value and DIVCLK_DIVIDE value,
will determine the output
frequency.
1 Specifies the division ratio for all
output clocks with respect to the
input clock. Effectively divides the
CLKIN going into the PFD.
0.0 Specifies the phase offset in
degrees of the clock feedback
output. Shifting the feedback clock
results in a negative phase shift of
all output clocks to the MMCM.
0.010 Allows specification of the
expected jitter on the reference
clock in order to better optimize
MMCM performance. A
bandwidth setting of OPTIMIZED
will attempt to choose the best
parameter for input clocking when
unknown. If known, then the value
provided should be specified in
terms of the unit interval (UI) (the
maximum peak to peak value) of
the expected jitter on the input
clock.
7 Series FPGAs Clocking Resources User Guide
UG472 (v1.5) July 13, 2012