Multi-Region Clock Buffer-Bufmr/Bufmrce; Bufmr Primitive - Xilinx 7 Series User Manual

Multi-Region Clock Buffer—BUFMR/BUFMRCE
The BUFMR replaces the multi-region/bank support for BUFR and BUFIO available in
previous Virtex architectures. There are two BUFMRs in every bank and each buffer can be
driven by one specific MRCC in the same bank. MRCC pins are labeled with MRCC in the
pin name for both the P and N pins of the pin pair (for example:
IO_L12N_T1_MRCC_12
banks and in the regions/banks above and below. BUFR and BUFIO primitives must be
separately instantiated. When using BUFR dividers (not in bypass), the BUFMR must be
disabled by deasserting the CE pin, the BUFR must be reset (cleared by asserting CLR), and
then the CE signal should be asserted. This sequence ensures that all BUFR output clocks
are phase aligned. If the dividers within the BUFRs are not used, then the circuit topology
only requires the use of BUFMR.
BUFMR inputs include:
•
•

BUFMR Primitive

BUFMRs
enable (CE). Deasserting CE stops the output clock. BUFMRs must drive BUFRs and
BUFIOs to route to the same region/bank and adjacent regions/banks. BUFMRs are
driven by the MRCCs or the GT clocks in the same region.
X-Ref Target - Figure 2-24
Table 2-9: BUFMR and BUFMRCE Port List and Definitions
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7 Series FPGAs Clocking Resources User Guide
UG472 (v1.5) July 13, 2012
). The BUFMRs drive the BUFIOs and/or BUFRs in the same region/
MRCCs in the same bank
GT clocks in the same region
(Figure 2-24, Table
Figure 2-24: BUFMR and BUFMRCE Primitives
Port Type
O Output
CE Input
I Input
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2-9, and Table 2-10) are a clock-in/clock-out buffer with clock
BUFMR
I
BUFMRCE
I
CE
ug472_c1_24_062210
Width
1
1
1
Regional Clocking Resources
IO_L12P_T1_MRCC_12
O
O
Definition
Clock output port
Output clock enable port
Clock input port
or
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