Xilinx 7 Series User Manual page 109

X-Ref Target - Figure B-2
Clock
Backbone
CE
BUFH
or
Left Side Clock
Connections
BUFG
CE
Figure B-2: Clock Region in Kintex-7 FPGAs with I/O Banks and no GT Transceivers (Right Side)
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7 Series FPGAs Clocking Resources User Guide
UG472 (v1.5) July 13, 2012
Fabric - Multiple Columns of CLB/Block RAM/DSP
CLB CLKA
CLKB
25 CLBs
CLB
5x36K
Block RAMs/
FIFOs
CLB
CLB
CLB
CLB
Horizontal Clocking Row
CLB
CLB
CLB
5x36K
CLB
Block RAMs/
FIFOs
CLB
25 CLBs
CLB
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CLK
10x
PLL/
DSP48
PHASER
Slices
10x
DSP48
MMCM
Slices
I/O Bank
SelectIO Logic
SelectIO Logic
SelectIO Logic
25 SelecIO
Logic Resources
BUFR BUFIO
SelectIO Logic
BUFIO/BUFR
Any I/O Clock CC
BUFMR
Any I/O Clock CC
BUFIO/BUFR
SelectIO Logic
BUFR BUFIO
25 SelectIO
Logic Resources
SelectIO Logic
SelectIO Logic
SelectIO Logic
UG472_aB_02_020812
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