Xilinx 7 Series User Manual page 58
Fpgas clocking resources
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- User manual (678 pages) ,
- User manual (74 pages)
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Chapter 2: Clock Routing Resources
X-Ref Target - Figure 2-28
From Local SLR
Clock Connection
HROW
From Local SLR
Clock Connection
HROW
From Local SLR
Clock Connection
HROW
Figure 2-28: SSI Technology Example for Virtex-7 XT Devices
www.BDTIC.com/XILINX
58
16 BUFGs
To SLR Global
Clock Network
16 BUFGs
Bidirectional 3-Stateable
Interposer Connection
16 BUFGs
To SLR Global
Clock Network
16 BUFGs
Bidirectional 3 Stateable
Interposer Connection
16 BUFGs
To SLR Global
Clock Network
16 BUFGs
Bidirectional 3-Stateable
Interposer Connection
www.xilinx.com
To SLR Global
Clock Network
SLR Clock Backbone
32
Super Logic Region
32 Interposer Clock
Backbone Connections
To SLR Global
Clock Network
SLR Clock Backbone
32
Super Logic Region
32 Interposer Clock
Backbone Connections
To SLR Global
Clock Network
SLR Clock Backbone
32
Super Logic Region
Interposer
7 Series FPGAs Clocking Resources User Guide
12 BUFHCEs
12 BUFHCEs
12 BUFHCEs
UG472_c1_28_020712
UG472 (v1.5) July 13, 2012
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