Appendix A: Multi-Region Clocking; Introduction - Xilinx 7 Series User Manual

Multi-Region Clocking

Introduction

Clocking and I/O interconnect logic across multiple clock regions in 7 series FPGAs is
different from how it was done in previous generations of Xilinx FPGAs. While the
increase in I/O and logic resources in a clock region has reduced the need for clock signals
to span multiple clock regions, these same wide I/O interfaces still demand the ability to
drive interconnect and I/O logic in more than one clock region. The 7 series FPGAs
BUFMR/BUFMRCE primitives enable clock-capable input pins to drive BUFIOs and
BUFRs in the region same region the input resides as well as the regions above and below.
This appendix details using the BUFIO and BUFR clock buffers to drive clock signals
across multiple clock regions.
All 7 series FPGAs are divided into areas known as clock regions. A clock region spans
from the global clocking column in the center of the device to either the left or right edge of
the device and is 50 rows of CLBs high
X-Ref Target - Figure A-1
www.BDTIC.com/XILINX
7 Series FPGAs Clocking Resources User Guide
UG472 (v1.5) July 13, 2012
7 Series FPGAs Architecture
Figure A-1: 7 Series Clocking Architecture Example
www.xilinx.com
Appendix A
(Figure A-1).
7 Series FPGAs Clock Region
ug472_aA_01_ 022811
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