Xilinx 7 Series User Manual page 78

Chapter 3: Clock Management Tile
DCLK – Dynamic Reconfiguration Reference Clock
The DCLK signal is the reference clock for the dynamic reconfiguration port. The rising
edge of this signal is the timing reference for all other port signals. The setup time is
specified in the data sheet. There is no hold time requirement for the other input signals
relative to the rising edge of the DCLK. The pin can be drive by an IBUF, IBUFG, BUFG,
BUFR, or BUFH. There are no dedicated connections to this clock input.
PSCLK – Phase-Shift Clock
This input pin provides the source clock for the dynamic phase-shift interface. All other
inputs are synchronous to the positive edge of this clock. The pin can be drive by an IBUF,
IBUFG, BUFG, BUFR, or BUFH. There are no dedicated connections to this clock input.
Not available in the PLL.
PSEN – Phase-Shift Enable
A dynamic (variable) phase-shift operation is initiated by synchronously asserting this
signal. It must be activated for one cycle of the PSCLK. After initiating a phase-shift the
phase is gradually shifted until a High pulse on PSDONE indicates that the operation is
complete. There are no glitches or sporadic changes during the operation. From the start to
the end of the operation the phase is shifted in a continuous analog manner. Not available
in the PLL.
PSINCDEC – Phase-Shift Increment/Decrement Control
This input signal synchronously indicates if the dynamic phase shift is an increment or
decrement operation (positive or negative phase-shift). PSENCDEC is asserted High for
increment and Low for decrement. There is no phase-shift overflow associated with the
dynamic phase shift operation. If more 360° or more are shifted, then the phase will simply
wrap around starting at the original phase. Not available in the PLL.
CLKOUT[0:6] – Output Clocks
These user-configurable clock outputs (CLKOUT0 through CLKOUT6 for the MMCM or
CLKOUT0 through CLKOUT5 for the PLL) can be divided versions of the VCO phase
outputs (user controllable) from 1 (bypassed) to 128. The input clock and output clocks can
be phase aligned.
When used with BUFR or BUFIO, only the MMCM can directly connect to the HPC from
the clock outputs CLKOUT0 through CLKOUT3. Additionally, CLKOUT0 through
CLKOUT3 can connect to the CMT backbone, for cascading MMCMs and PLLs. Similar to
driving MMCMs and PLLs from the CCIO pins to adjacent regions (see
Inputs), cascading uses some of the limited resources available in the CMT backbone to
connect clocking resources directly in adjacent regions. A phase offset between the
cascaded elements within the same column will also result.
For possible configurations see
and CLKFBOUT can be used in fractional divide mode. All CLKOUT outputs can be used
in non-fractional mode to provide a static or dynamic phase shift. In fractional mode, only
fixed phase-shift is allowed. See
CLKOUT[0:3]B – Inverted Output Clocks
Inverted (180° phase shift) of CLKOUT[0:3]. Not available in the PLL.
www.BDTIC.com/XILINX
78
MMCM and PLL Use
Static Phase Shift Mode
www.xilinx.com 7 Series FPGAs Clocking Resources User Guide
Clock-Capable
Models. In the MMCM, CLKOUT0
for more information.
UG472 (v1.5) July 13, 2012