Using The Optional Management Interface; Host Clock Frequency - Xilinx LogiCORE IP MAC v8.5 User Manual

Ug144 1-gigabit ethernet
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Configuration and Status
This chapter provides general guidelines for configuring and monitoring the GEMAC
core, including a detailed description of the client-side management interface and registers
present in the core. It also describes the alternative to the optional management interface
which is the Configuration Vector.

Using the Optional Management Interface

The Management Interface is a processor-independent interface with standard address,
data, and control signals. It may be used as is, or a wrapper (not supplied) may be used to
interface to common bus architectures. For port definition, see
(Optional)," on page
This interface is used for:
The Management Interface can be accessed in different ways, depending on the type of
transaction. A truth table showing which access method is required for each transaction
type is shown in
Table 8-1: Management Interface Transaction Types

Host Clock Frequency

The Management Interface clock, host_clk, is used to derive the MDIO clock, mdc, and
for this reason is subject to the following frequency restriction:
Configuring the GEMAC core to derive the mdc signal from this clock is detailed in
Interface," on page
1-Gigabit Ethernet MAC v8.5 User Guide
UG144 April 24, 2009
-- DISCONTINUED PRODUCT --
28.
Configuring of the GEMAC core via the configuration registers.
Access through the MDIO interface to the management registers located in the PHY
connected to the GEMAC core.
Table
8-1. These access methods are described in the following sections.
Transaction
Configuration
MIIM access
≥ 10 MHz
86.
www.xilinx.com
host_miim_sel
0
1
Chapter 8
"Management Interface
host_addr[9]
1
X
"MDIO
77

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