Key Differences From Spartan-6 Fpgas - Xilinx 7 Series User Manual

Chapter 1: Clocking Overview
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Key Differences from Spartan-6 FPGAs

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Spread Spectrum support has been added to the MMCMs.
Some of the Spartan-6 FPGA clocking circuit topologies, functions, and blocks that are
unique to the Spartan-6 architecture are not supported and have been replaced by the
7 series FPGAs clocking features. Features and functions such as DCM_SP,
DCM_CLKGEN, BUFIO2, BUFIO2_2CLK, BUFIO2FB, BUFPLL, and BUFPLL_MCB
are not directly supported in 7 series devices.
The PLL is a subset of the MMCM with the same performance (except minimum
CLKIN/PFD and minimum/maximum VCO frequencies), some connectivity
limitations, and some reduced functionality. When compared to previous Spartan
FPGA PLLs, the 7 series FPGAs PLLs add power down, input clock switching, and
cascading to adjacent CMTs. The PLLs do not have a direct connection to the BUFIO
or BUFR.
In the 7 series FPGAs, there is no direct replacement for the BUFIO2 and
BUFIO2_2CLK primitives. Use the BUFIO and BUFR instead with the recommended
connections to drive the ILOGIC and OLOGIC.
The Spartan-6 FPGA BUFIO2 dedicated input routing from GCLKs to the CMT and
global clock buffers are no longer supported. To migrate to the 7 series FPGAs, use the
dedicated input routing from the CCIO pins.
There is no direct equivalent in the 7 series FPGAs to the Spartan-6 FPGA BUFPLL. To
migrate, use the BUFIO and BUFR with the recommended connections to the ILOGIC
and OLOGIC. The high-performance clock routing from MMCME2 CLKOUT[0:3]
replaces the dedicated routing to the BUFPLL. The ISERDES and OSERDES circuitry
is based on the Virtex-6 architecture. See UG471: 7 Series FPGAs SelectIO Resources User
Guide.
In the 7 series FPGAs, the BUFPLL_MCB primitive is no longer required. DDR
memory interfaces have a different (soft) implementation in the 7 series FPGAs.
Consult the UG586: Memory Interface Solutions User Guide.
In the 7 series FPGAs, the BUFIO2FB primitive is no longer required. For MMCM and
PLL feedback connections the CLKFBIN can be directly connected to global clock
buffers, input pins, or CLKFBOUT depending on the feedback used.
Spartan-6 FPGAs only supported BUFH. The 7 series FPGAs BUFHCE primitive adds
the ability to disable the clock for potential power savings in the clock region driven
by this resource.
The 7 series FPGAs new buffers, BUFMR/BUFMRCE, drive BUFIOs and/or BUFRs in
the same and vertically adjacent clock regions. When used with a BUFIO or BUFR,
BUFMR/BUFMRCE allow MRCC inputs to access BUFIO and BUFR in adjacent clock
regions. BUFMRCE has a selectable synchronous or asynchronous switching feature.
A new primitive for Spartan-6 FPGA design migration is the BUFR. When used in
conjunction with BUFIO the BUFRs functionality replaces the BUFIO2,
BUFIO2_2CLK, and BUFPLL capabilities. There are four BUFRs in each clock region.
Another new primitive for Spartan-6 FPGA design migration is the BUFIO. When
used with the BUFR, the BUFIO functionality replaces the BUFIO2, BUFIO2_2CLK,
and BUFPLL capabilities. There are four BUFIOs per bank.
Instead of one DCM and one PLL in the Spartan-6 architecture, the 7 series FPGAs use
a CMT that contains one MMCM, one PLL, and dedicated memory interface logic
which is reserved for Xilinx use at this time. DCMs and their associated capabilities
are now supported with these functions. The CMTs are located in a separate column
www.xilinx.com 7 Series FPGAs Clocking Resources User Guide
UG472 (v1.5) July 13, 2012