Xilinx 7 Series User Manual page 12

Chapter 1: Clocking Overview
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Each 7 series device has 32 global clock lines that can clock and provide control signals to
all sequential resources in the whole device. Global clock buffers (BUFGCTRL, simplified
as BUFG throughout this user guide) drive the global clock lines and must be used to
access global clock lines. Each clock region can support up to 12 of these global clock lines
using the 12 horizontal clock lines in the clock region.
The global clock buffers:
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The horizontal clock buffer (BUFH/BUFHCE) allows access to the global clock lines in a
single clock region through the horizontal clock row. It can also be used as a clock enable
circuit (BUFHCE) to independently enable or disable clocks that span a single clock region.
Each clock region can support up to 12 clocks using the 12 horizontal clock lines in each
clock region.
Each 7 series FPGA has regional and I/O clock trees that can clock all sequential resources
in one clock region. Each device also has multi-clock region buffers (BUFMR) that allow
regional and I/O clocks to span up to three vertically adjacent clock regions.
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High-performance clock routing connects certain outputs of the CMT to the I/O on a very
low jitter, minimal duty-cycle distorted direct path.
Chapter 2, Clock Routing
clocks. It also describes which clock routing resources to utilize for various applications.
www.BDTIC.com/XILINX
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CMTs within the same clock region and, with limitations, vertically adjacent clock
regions
Can be used as a clock enable circuit to enable or disable clocks that span multiple
clock regions
Can be used as a glitch-free multiplexer to:
• select between two clock sources
• switch away from a failed clock source
Are often driven by a CMT to:
• eliminate the clock distribution delay
• adjust clock delay relative to another clock
The I/O clock buffer (BUFIO) drives the I/O clock tree, providing access to clock all
sequential I/O resources in the same I/O bank.
The regional clock buffer (BUFR) drives regional clock trees that drive all clock
destinations in the same clock region and can be programmed to divide the incoming
clock rate.
In conjunction with the programmable serializer/deserializer in the IOB (refer to the
"Advanced SelectIO Logic Resources" chapter in UG471, 7 Series FPGAs SelectIO
Resources User Guide), the BUFIO and BUFR clock buffers allow source-synchronous
systems to cross clock domains without using additional logic resources.
The regional and I/O clock trees in adjacent clock regions and I/O banks can be
driven using the multi-clock region buffer (BUFMR) when used with the associated
BUFR or BUFIO.
Up to four unique I/O clocks and four unique regional clocks can be supported in one
clock region or I/O bank.
Resources, has further details on global, regional, and I/O
www.xilinx.com 7 Series FPGAs Clocking Resources User Guide
UG472 (v1.5) July 13, 2012