Use Cases - Xilinx 7 Series User Manual

X-Ref Target - Figure A-3
Every BUFMR is capable of driving the BUFRs and BUFIOs in the same region and the
regions directly above and below. BUFMRs are driven by CCIO or gigabit-transceiver (GT)
outputs in the same clock region. This allows the CCIO and GT output clocks to span
multi-regions using the same circuit topology. Of the four CCIOs present in every clock
region, two can drive BUFMRs. These pins are labeled as MRCC to denote their
multi-region ability. The two CCIOs that cannot drive BUFMRs are labeled as SRCC for
single-region CCIO. Every MRCC pin has a master or P-side and a slave or N-side. When
using a MRCC pin to drive a BUFMR, use only the master or P-side. To identify the master
or P-side, look for a P in the pin name (for example: IO_LxxP_Tx_MRCC_xx).
The GT inputs to the Virtex®-6 FPGA BUFRs are not available in the 7 series FPGAs
architecture. The BUFMR, however, can get its inputs from any one of the GT clocks within
the clock region. This allows the GT clocks to span multi-regions using the same circuit
topology as shown in
super-logic regions (SLRs) on the devices using stacked-silicon interconnect technology.

Use Cases

When using BUFMRs to drive logic in multiple regions, group the logic being driven by
the multiple BUFRs or BUFIOs into (up to three) subsets, each with a separate BUFR or
BUFIO. Creating AREA_GROUP constraints helps to group this logic together. These
constraints can be entered into the UCF directly or automatically using the PlanAhead™
tool.
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www.BDTIC.com/XILINX
7 Series FPGAs Clocking Resources User Guide
UG472 (v1.5) July 13, 2012
Horizontal
Clock Row
BUFMR
CMT Column
Figure A-3: BUFMR Primitive
Figure A-3. Also, BUFMRs cannot cross the boundary between
In the PlanAhead flow, select the logic to be grouped in the netlist view of the tool,
right-click, and select Draw Pblock.
Choose an area where the logic must be constrained. For more information on
constraining logic in the PlanAhead tool, refer to the PlanAhead tutorials at:
www.xilinx.com > Documentation > Design Tools > PlanAhead
www.xilinx.com
PLL
SRCC
MRCC
MRCC
SRCC
MMCM
I/O Column
Use Cases
Serial
Transceiver
Clocks
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