Summary Of Clock Connectivity - Xilinx 7 Series User Manual

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Summary of Clock Connectivity

Table 1-1
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7 Series FPGAs Clocking Resources User Guide
UG472 (v1.5) July 13, 2012
adjacent to the SelectIO columns and have dedicated access to the I/O. DCM_SP and
DCM_CLKGEN are no longer available and their functionality is now supported in
the MMCMs and PLLs.
Global clock (GCLK) inputs are no longer supported in the 7 series FPGAs. Four
clock-capable input pins are now available in every bank that support much of the
Spartan-6 FPGA GCLK pin capabilities.
To Spartan-6 FPGA designers, the MMCM is a new functional block. The MMCM
adds fractional divide, fine phase shifting, dynamic phase shifting, inverted clock
outputs, CLKOUT6 to CLKOUT4 cascading, and some other features. The direct
routing connection to the BUFPLL is replaced by the high-performance path (HPC)
connection from the MMCMs to the BUFIO/BUFR using CLKOUT[0:3]. A more
extensive DRP is also available.
Using the PLL is no longer the recommended CMT function for general-purpose
high-speed I/O clocking. The PLL does not have a direct connection to the BUFIO or
BUFR. CLKOUT0 feedback is no longer supported. Use the MMCM for high-speed
I/O interfaces. Cascade connections use limited CMT backbone resources. There is
also a new power down mode. Input clock switching is fully supported. Operating
ranges are different between the Spartan-6 FPGAs and the 7 series FPGAs. The DRP
functionality is still available. The DRP functional locations and addresses have
changed.
The Spartan-6 FPGAs DCM_SP is no longer supported. To migrate to the 7 series
FPGAs, use the MMCM and PLL.
The Spartan-6 FPGAs DCM_CLKGEN is not directly supported in the 7 series FPGAs.
Use MMCM or PLL with low bandwidth for input jitter filtering. Dynamic
reprogramming of the M/D values can also be accomplished using the DRP reference
design for the MMCM or PLL.
summarizes the 7 series FPGAs clock connectivity.
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Summary of Clock Connectivity
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