Mmcm With Internal Feedback - Xilinx 7 Series User Manual

There are certain restrictions on implementing the feedback. The CLKFBOUT output can
be used to provide the feedback clock signal. When an MMCM is driving both BUFGs and
BUFH, only one of the clock buffers that is also used in the feedback path is deskewed. The
fundamental restriction is that both input frequencies to the PFD must be identical.
Therefore, the following relationship must be met:
As an example, if ƒ
clock output frequency is 498 MHz. Since the M value in the feedback path is 6, both input
frequencies at the PFD are 166 MHz.
In another more complex scenario has an input frequency of 66.66 MHz and D = 2, M = 30,
and O = 4. The VCO frequency in this case is 1000 MHz and the CLKOUT output
frequency is 250 MHz. Therefore, the feedback frequency at the PFD is 1000/30 or
33.33 MHz, matching the 66.66 MHz/2 input clock frequency at the PFD.

MMCM with Internal Feedback

The MMCM feedback can be internal to the MMCM when the MMCM is used as a
synthesizer or jitter filter and there is no required phase relationship between the MMCM
input clock and the MMCM output clock. The MMCM performance increases because the
feedback clock is not subjected to noise on the core supply since it never passes through a
block powered by this supply. Of course, noise introduced on the CLKIN signal and the
BUFG will still be present
X-Ref Target - Figure 3-13
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7 Series FPGAs Clocking Resources User Guide
UG472 (v1.5) July 13, 2012
f f
IN VCO
------ - = f = ------------ -
FB
D M
is 166 MHz, D = 1, M = 6, and O = 2, then VCO is 996 MHz and the
IN
(Figure 3-13).
IBUFG
CLKOUT0
CLKIN1
CLKFBIN CLKOUT0B
RST
CLKOUT1
CLKOUT1B
CLKOUT2
CLKOUT2B
CLKOUT3B
CLKOUT4
CLKOUT5
CLKOUT6
CLKFBOUT
CLKFBOUTB
LOCKED
MMCM
Figure 3-13: MMCM with Internal Feedback
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MMCM and PLL Use Models
Equation 3-11
BUFG
To Logic
UG472_c2_12_061710
89