Driving Multiple Bufrs; Multiple Buffers Per Clock Region; Driving Multiple Bufrs (With Divide) And Bufio - Xilinx 7 Series User Manual

Driving Multiple BUFRs

When driving interconnect logic and I/O logic at the same clock rate from the same clock
source across three clock regions, use a BUFMRCE primitive (multi-region clock buffer
with clock enable). For more information on BUFMRCEs, see
Chapter
logic and I/O logic
subsets, each driven by its own BUFR.
X-Ref Target - Figure A-5
If the divide value in the BUFR is being used, then all BUFR instances must be reset while
the BUFMRCE is disabled. See
described in
buffers in the appropriate location.

Multiple Buffers Per Clock Region

Driving Multiple BUFRs (with Divide) and BUFIO

When driving the ISERDES/OSERDES CLK and CLKDIV pins, use BUFIOs in conjunction
with BUFRs that have their divide capability activated. The BUFIO drives a clean,
low-skew clock to the CLK port of the ISERDES/OSERDES and the BUFR drives the
slower CLKDIV input. For example in
the FPGA on a MRCC pin, the BUFIO drives the CLK input at the full rate of 250 MHz and
the BUFR with BUFR_DIVIDE=2 drives the CLKDIV inputs at the half rate of 125 MHz.
When driving multiple buffers in this manner, manually place the buffers with a LOC
constraint. The logic driven by the buffers is automatically placed in the appropriate
location.
www.BDTIC.com/XILINX
7 Series FPGAs Clocking Resources User Guide
UG472 (v1.5) July 13, 2012
2. A BUFMRCE can drive three BUFRs which, in turn, drive both interconnect
(Figure A-5). Group the logic clocked by the three BUFRs into separate
Software Automatically Places
Clock Region Boundary
MRCC
RST
Clock Region Boundary
Figure A-5: Driving Multiple BUFRs
Figure A-4 and
www.xilinx.com
BUFMRCE
BUFR Alignment
Circuit
BUFR Alignment for more details. In the use cases
Figure A-5, the placer software automatically places the
Figure A-6, when a 250 MHz input clock comes in to
Use Cases
BUFMR Primitive in
Interconnect
Logic and
I/O Logic
BUFR
Interconnect
Logic and
I/O Logic
BUFR
Interconnect
Logic and
I/O Logic
BUFR
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