Mmcme2_Base And Plle2_Base Primitives - Xilinx 7 Series User Manual

Chapter 3: Clock Management Tile
The two 7 series FPGAs PLL primitives, PLLE2_BASE and PLLE2_ADV, are shown in
Figure
X-Ref Target - Figure 3-5

MMCME2_BASE and PLLE2_BASE Primitives

The MMCME2_BASE primitive provides access to the most frequently used features of a
stand alone MMCM. Clock deskew, frequency synthesis, coarse phase shifting, and duty
cycle programming are available to use with the MMCME2_BASE. The ports are listed in
Table
Table 3-1: MMCME2_BASE Ports
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66
3-5.
CLKIN1 CLKOUT0
CLKOUT1
CLKOUT2
CLKFBIN
CLKOUT3
RST
CLKOUT4
PWRDWN
CLKOUT5
CLKFBOUT
LOCKED
PLLE2_BASE
3-1.
Description
Clock Input
Control Inputs
Clock Output
Status and Data Outputs
Power Control
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Figure 3-5: PLL Primitives
Ports
CLKIN1, CLKFBIN
RST
CLKOUT0 to CLKOUT6, CLKOUT0B to CLKOUT3B,
CLKFBOUT, and CLKFBOUTB
LOCKED
PWRDWN
7 Series FPGAs Clocking Resources User Guide
CLKIN1 CLKOUT0
CLKIN2 CLKOUT1
CLKFBIN CLKOUT2
CLKOUT3
RST
CLKOUT4
CLKINSEL
CLKOUT5
DADDR[4:0]
DI[15:0] CLKFBOUT
DWE
DEN
DCLK
LOCKED
PWRDWN
DO[15:0]
DRDY
PLLE2_ADV
UG472_c2_05_112310
UG472 (v1.5) July 13, 2012