Clocking Across Multiple Regions; Bufmr Primitive - Xilinx 7 Series User Manual

Appendix A: Multi-Region Clocking
Each clock region has its own resources. The horizontal clock row
middle of the clock region with 25 rows of CLBs above and 25 rows of CLBs below. The I/
O column that resides in each clock region is 50 I/O high and is exactly one I/O bank.
There are four clock-capable input (CCIO) pins located in the I/O bank within each clock
region, two above the horizontal clock row and two below.
X-Ref Target - Figure A-2

Clocking Across Multiple Regions

While the increase in logic and I/O resources within a clock region reduces the need for
designs to span multiple clock regions, some designs still require larger I/O interfaces to
drive the same clock signal from an input source across multiple clock regions. Without
using any other primitives, a clock signal entering the device on a CCIO pin can only drive
the BUFRs and/or BUFIOs within the same region. Some design require the incoming
clock signal to clock interconnect logic (such as slice flip-flops, block RAM and DSP slices)
and I/O logic (such as ISERDES, OSERDES, ILOGIC, OLOGIC, IDELAY and ODELAY) in
more than one clock region. To accomplish this, the BUFMR primitive must be used.

BUFMR Primitive

The BUFMR primitive is a multi-region clock buffer that allows clock signals to access
BUFRs and BUFIOs in regions above and below the region where the clock signal enters
the device. BUFMRs can span more than one clock region
BUFMRs located in each clock region. The BUFMRs drive the dedicated low-skew clocking
resources residing within the CMT column, ensuring that the least possible skew is
inserted when driving clock signals into multiple regions.
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100
Horizontal
Clock Row
CMT Column
Figure A-2: Clock Region Resources
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(Figure
PLL
CCIO
CCIO
MMCM
(Figure A-3). There are two
7 Series FPGAs Clocking Resources User Guide
UG472 (v1.5) July 13, 2012
A-2) sits in the
I/O Column
ug472_aA_02_022811