Xilinx 7 Series User Manual page 81

Table 3-7: MMCM Attributes (Cont'd)
Attribute
CLKIN1_PERIOD
CLKIN2_PERIOD
CLKFBOUT_USE_FINE_PS Boolean FALSE, TRUE
CLKOUT0_USE_FINE_PS
CLKOUT[1:6]_USE_FINE_PS
STARTUP_WAIT
CLKOUT4_CASCADE
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7 Series FPGAs Clocking Resources User Guide
UG472 (v1.5) July 13, 2012
Type Allowed Values
Real 0.938 to 100.000
Real 0.938 to 100.000
Boolean FALSE, TRUE
Boolean FALSE, TRUE
Boolean FALSE, TRUE
Boolean FALSE, TRUE
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General Usage Description
Default Description
0.000 Specifies the input period in ns to
the MMCM CLKIN1 input.
Resolution is down to the ps. This
information is mandatory and
must be supplied.
0.000 Specifies the input period in ns to
the MMCM CLKIN2 input.
Resolution is down to the ps. This
information is mandatory and
must be supplied.
FALSE CLKFBOUT counter variable fine
phase shift enable.
FALSE CLKOUT0 counter variable fine
phase shift enable.
CLKOUT0_DIVIDE must be an
integer and therefore fractional
divide is not allowed.
FALSE CLKOUT[1:6] variable fine phase
shift enable.
FALSE Wait during the configuration
startup cycle for the MMCM to
lock.
FALSE Cascades the output divider
(counter) CLKOUT6 into the input
of the CLKOUT4 divider for an
output clock divider that is greater
than 128, effectively providing a
total divide value of 16,384.
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