Digital Outputs From Analog Inputs - Xilinx MIcroBlaze Development Spartan-3E 1600E Kit User Manual

Chapter 10: Analog Capture Circuit
REFAB
REFCD

Digital Outputs from Analog Inputs

The analog capture circuit converts the analog voltage on VINA or VINB and converts it to
a 14-bit digital representation, D[13:0], as expressed by
The GAIN is the current setting loaded into the programmable pre-amplifier. The various
allowable settings for GAIN and allowable voltages applied to the VINA and VINB inputs
appear in
The reference voltage for the amplifier and the ADC is 1.65V, generated via a voltage
divider shown in
VINA or VINB.
The maximum range of the ADC is 1.25V, centered around the reference voltage, 1.65V.
Hence, 1.25V appears in the denominator to scale the analog input accordingly.
Finally, the ADC presents a 14-bit, two's complement digital output. A 14-bit, two's
complement number represents values between -2
scaled by 8192, or 2
See
pre-amplifier.
76
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Header J7
(3.3V)
LTC 6912-1 AMP
(2.5V)
VINA
VINB
GND
VCC
(3.3V)
REF = 1.65V
Spartan-3E FPGA
SPI_MOSI
(N10) (T4)
(E18) (N7)
AMP_CS
(U16)
SPI_SCK
AMP_SHDN
(P7)
AD_CONV
(P11)
AMP_DOUT
SPI_MISO
Figure 10-2: Detailed View of Analog Capture Circuit
D 13:0 =
Table 10-2.
Figure 10-2. Consequently, 1.65V is subtracted from the input voltage on
13
.
"Programmable Pre-Amplifier"
MicroBlaze Development Kit Spartan-3E 1600 Edition User Guide
–
A
+
–
B
+
DIN 0 1 2 3 0 1 2 3 DOUT
A GAIN B GAIN
CS/LD
SPI Control Interface
SCK
SHDN
V – 1.65V
IN
----------------------------------- -
GAIN 8192
1.25V
13
and 2
to control the GAIN settings on the programmable
LTC 1407A-1 ADC
+
A/D
–
Channel 0
14
+
A/D
–
Channel 1
14
0 ... 13 0 ...
CHANNEL 1 CHANNEL 0
SPI Control Interface
SCK
CONV
UG257_10_02_060706
Equation 10-1.
Equation 10-1
13
-1. Therefore, the quantity is
UG257 (v1.1) December 5, 2007
R
13 SDO