Cmt Overview; Clock Buffers, Management, And Routing - Xilinx 7 Series User Manual

CMT Overview

Each 7 series FPGA has up to 24 CMTs, each consisting of one MMCM and one PLL. The
MMCMs and PLLs serve as frequency synthesizers for a wide range of frequencies, serve
as a jitter filters for either external or internal clocks, and deskew clocks. The PLL contains
a subset of the MMCM functions. The 7 series FPGA clock input connectivity allows
multiple resources to provide the reference clock(s) to the MMCM and PLL.
7 series FPGAs MMCMs have infinite fine phase-shift capability in either direction and can
be used in dynamic phase-shift mode. MMCMs also have a fractional counter in either the
feedback path or in one output path, enabling further granularity of frequency synthesis
capabilities.
The LogiCORE IP clocking wizard is available to assist in utilizing MMCMs and PLLs to
create clock networks in 7 series FPGA designs. The GUI interface is used to collect clock
network parameters. The clocking wizard chooses the appropriate CMT resource and
optimally configures the CMT resource and associated clock routing resources.
Chapter 3, Clock Management
connectivity.

Clock Buffers, Management, and Routing

The figures in this section provide a visual and layered explanation of the 7 series FPGAs
clock architecture.
Figure 1-1
clocking center line (the clock backbone) divides the device into adjacent left and right
regions while the horizontal center line divides the device into its top and bottom sides.
The resources in the clock backbone are mirrored to both sides of the horizontally adjacent
regions, thus extending certain clock resources into the horizontal adjacent region. The top
and bottom division separates two sets of global clock buffers (BUFGs) and imposes some
limitations on how they can be connected. However, BUFGs do not belong to a clock
region and can reach any clocking point on the device. All horizontal clock resources are
contained in the center of the clock region's horizontal clock row (HROW), and vertical,
non-regional clock resources are contained in either the clock backbone or CMT backbone.
www.BDTIC.com/XILINX
7 Series FPGAs Clocking Resources User Guide
UG472 (v1.5) July 13, 2012
Tile, has further details on the CMT block features and
is a high-level view of the 7 series FPGAs clocking architecture. The vertical
www.xilinx.com
Clocking Architecture Overview
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