Xilinx 7 Series User Manual page 18

Chapter 1: Clocking Overview
X-Ref Target - Figure 1-5
Each I/O bank contains four BUFIOs and four BUFRs. Each of these clock buffers can be
driven by a specific CC input clock pin pair or can be driven directly by a specific output
clock of the MMCM. Two of the CC input pin pairs, called MRCCs, support a multi-region
clocking scheme. An MRCC pin pair can drive a specific BUFMR, which in turn can drive
BUFIOs and BUFRs in the same and adjacent regions facilitating multi-region/bank
interfaces. Similarly, a GT quad can also drive the BUFMRs. The MMCM<3:0> outputs
have a dedicated high-performance differential path to the BUFRs and BUFIOs. This
feature is also referred to as high-performance clocks (HPC) in this document.
Although all 7 series devices have the same fundamental architecture, there are some
architectural differences between the families and devices within families. Every 7 series
FPGA has a minimum of one complete I/O column on the left edge of the device. A GT can
be any one of the serial transceivers supported by the 7 series FPGAs (GTP, GTX, or GTH).
Devices with GTs either have a mixed column of GTs and I/Os to the right edge of the
device (some Kintex-7 and some Artix-7 devices) or have a complete column of GTs to the
right edge (some Kintex-7 and some Virtex-7 devices) and a complete I/O column on the
right side of the device. Other Virtex-7 devices have complete GT columns on the left and
right edges with a complete I/O column in the left and right sides. The two larger Artix
devices have GTP transceivers on the top and bottom next to the clocking column.
Therefore, not all clock regions in the 7 series devices contain all the blocks shown in the
above figures. For a block-level architectural view of the various 7 series devices, see the
www.BDTIC.com/XILINX
18
Fabric
Clock
Backbone
4
HROW
BUFG
BUFH
4
Figure 1-5: BUFR/BUFMR/BUFIO Clock Region Detail
www.xilinx.com
I/O
4
Bank
2
CMT
BUFR
Column
PLL
BUFMR
BUFMR
<0>
<1>
<2>
<3>
BUFR
MMCM
CMT
Backbone
7 Series FPGAs Clocking Resources User Guide
4 4
Fabric
BUFIO
SRCC
Pair
MRCC
Pair
GT
Quad
MRCC
Pair
SRCC
Pair
BUFIO
UG472_c1_34_020712
UG472 (v1.5) July 13, 2012