Xilinx 7 Series User Manual page 91

MMCM. This path provides the lowest device jitter. Cascading using the inverted
CLKOUTxB outputs is not available.
f = f
OUTMMCM2 OUTMMCM1
X-Ref Target - Figure 3-15
IBUFG
CLKIN1
CLKFBIN
RST
MMCM
Figure 3-15: Cascading Two MMCMs Without Any Clock Alignment
X-Ref Target - Figure 3-16
IBUFG
CLKIN1
CLKFBIN
RST
MMCM
Figure 3-16: Cascading Two MMCMs With the Closest Possible Clock Alignment
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7 Series FPGAs Clocking Resources User Guide
UG472 (v1.5) July 13, 2012
M
MMCM2
------------------------------------------------- - = f
×
IN
D O
MMCM2 MMCM2
CLKOUT0
BUFG
CLKOUT0B
CLKOUT1
CLKOUT1B
CLKOUT2
CLKOUT2B
CLKOUT3B
CLKOUT4
CLKOUT5
CLKOUT6
CLKFBOUT
CLKFBOUTB
LOCKED
Uncompensated Delay
CLKOUT0
BUFG
CLKOUT0B
CLKOUT1
CLKOUT1B
CLKOUT2
CLKOUT2B
CLKOUT3B
CLKOUT4
CLKOUT5
BUFG
CLKOUT6
CLKFBOUT
CLKFBOUTB
LOCKED
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M
MMCM1
×
------------------------------------------------- - ------------------------------------------------- -
×
D O D
MMCM1 MMCM1 MMCM2
CLKOUT0
CLKIN1
CLKFBIN
CLKOUT0B
RST
To Logic
CLKOUT1
CLKOUT1B
CLKOUT2
CLKOUT2B
CLKOUT3B
CLKOUT4
CLKOUT5
CLKOUT6
CLKFBOUT
CLKFBOUTB
MMCM
CLKOUT0
CLKIN1
CLKFBIN
CLKOUT0B
RST
To Logic
CLKOUT1
CLKOUT1B
CLKOUT2
CLKOUT2B
CLKOUT3B
CLKOUT4
CLKOUT5
CLKOUT6
To Logic
CLKFBOUT
CLKFBOUTB
MMCM
MMCM and PLL Use Models
M
MMCM2
Equation 3-12
×
O
MMCM2
BUFG
To Logic
LOCKED
ug472_c2_14_061710
BUFG
To Logic
LOCKED
ug472_c2_15_042611
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