Xilinx 7 Series User Manual page 4

Date Version
02/16/12 1.4
(Cont'd)
07/13/12 1.5
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7 Series FPGAs Clocking Resources User Guide
In introductory paragraph of
connecting to OSERDES and buffers. Replaced cross reference to UG429, 7 Series FPGAs
Migration Methodology Guide, with UG872, Large FPGA Methodology Guide. Updated
Stacked Silicon Interconnect
Figure 2-30.
Removed hold block from
Only Using Integer Divide. Replaced 64 with 63 in
Fine Phase Shift in Fixed or Dynamic Mode in the
LOCKED in Table 3-5. Updated LOCKED. In
values of CLKOUT[0]_DIVIDE_F and CLKFBOUT_MULT_F, and description of
STARTUP_WAIT and COMPENSATION. In
updated description of COMPENSATION. Replaced GTX with GT in
Updated Dynamic Reconfiguration
Added Appendix B, Clocking Resources and Connectivity Variations per Clock
Updated paragraph after Figure
Key Differences from Virtex-6
IBUFDS_GTE2.O/IBUFDS_GTE2.ODIV2 pin from
Updated note 5 in Table 2-1. Added
Updated last sentence of Introduction. Updated
Output Bus. Added SS_EN, SS_MODE, and SS_MOD_PERIOD to
Spread-Spectrum Clock Generation.
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Revision
High-Performance Clocks, removed description of HPCs
Clocking. Replaced SRL with SLR in
Figure 3-2. Updated clock frequencies in
Equation
MMCM. Updated pin description of
Table 3-7, updated type and allowed
Table 3-8, added STARTUP_WAIT and
Port.
1-4. Added bullet about spread spectrum support to
FPGAs. Updated BUFG and BUFH pins, and removed
Table
Figure 2-28.
DO[15:0] – Dynamic Reconfiguration
Figure 2-28. Added
Frequency Synthesis
3-4. Updated Interpolated
Figure 3-10.
Region.
1-1. Updated Table 1-2.
Table 3-7. Added
UG472 (v1.5) July 13, 2012