Mmcms And Plls - Xilinx 7 Series User Manual

Chapter 3: Clock Management Tile
X-Ref Target - Figure 3-1

MMCMs and PLLs

7 series devices contain up to 24 CMT tiles. The MMCMs and PLLs serve as frequency
synthesizers for a wide range of frequencies, serve as a jitter filters for either external or
internal clocks, and deskew clocks.
The PLL in the 7 series FPGAs, a subset of the MMCM functionality, is based on the
MMCM and not necessarily based on previous PLL designs. The additional features
supported by the MMCM are:
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Input multiplexers select the reference and feedback clocks from either the IBUFG, BUFG,
BUFR, BUFH, GTs (CLKIN only), or interconnect (not recommended). Each clock input has
a programmable counter divider (D). The phase-frequency detector (PFD) compares both
phase and frequency of the rising edges of both the input (reference) clock and the
feedback clock. If a minimum High/Low pulse is maintained, the duty cycle is ancillary.
The PFD is used to generate a signal proportional to the phase and frequency between the
two clocks. This signal drives the charge pump (CP) and loop filter (LF) to generate a
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BUFR
IBUFG (CC)
BUFG
GT
BUFH
Local Routing
(not recommended)
Figure 3-1: Block Diagram of the 7 Series FPGAs CMT
Direct HPC to BUFR or BUFIO using CLKOUT[0:3]
Inverted clock outputs (CLKOUT[0:3]B)
CLKOUT6
CLKOUT4_CASCADE
Fractional divide for CLKOUT0_DIVIDE_F
Fractional multiply for CLKFBOUT_MULT_F
Fine phase shifting
Dynamic phase shifting
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CLKIN1
CLKIN2
PLL
CLKFB
CLKIN1
CLKIN2
MMCM
CLKFB
7 Series FPGAs Clocking Resources User Guide
UG472 (v1.5) July 13, 2012
BUFG
BUFH
BUFG
BUFH
ug472_c2_01_032511