Xilinx 7 Series User Manual page 45

X-Ref Target - Figure 2-15
X-Ref Target - Figure 2-16
In
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7 Series FPGAs Clocking Resources User Guide
UG472 (v1.5) July 13, 2012
Asynchronous MUX
Design Example
I1
I0
S
Figure 2-15: Asynchronous MUX with BUFGCTRL Design Example
I1
I0
S
O
at I0
Figure 2-16: Asynchronous MUX Timing Diagram
Figure 2-16:
The current clock is from I0.
S is activated High.
The Clock output immediately switches to I1.
When Ignore signals are asserted High, glitch protection is disabled.
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IGNORE1
V
DD
CE1
V
DD
S S1
I1
O
I0
S0
CE0
V
DD
IGNORE0
V
DD
T T
BCCKO_O BCCKO_O
Begin I1
Global Clocking Resources
O
ug472_c1_15_061310
UG472_c1_16_033011
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