Global Clocking Resources; Clock Tree And Nets - Gclk - Xilinx 7 Series User Manual

X-Ref Target - Figure 2-1
XC7K160T
Bank 16
HR
Bank 15
HR
Top BUFGs
Bottom BUFGs
Bank 14
HR
Bank 13
HR
Bank 12
HR
Figure 2-1: Center Alignment Example using XC7K325T and XC7K160T Devices
There can also be situations when migrating to a smaller device in the same package where
all BUFGs in the larger device's south side are already utilized and no more BUFGs are
available. See UG475: 7 Series FPGAs Packaging and Pinout Specification for BUFG and I/O
bank alignments.
Additionally, devices with multiple super logic regions (SLRs) can have similar restrictions
when migrating to/from monolithic paths in a single SLR in the same package.

Global Clocking Resources

Global clocks are a dedicated network of interconnect specifically designed to reach all
clock inputs to the various resources in an FPGA. These networks are designed to have low
skew and low duty cycle distortion, low power, and improved jitter tolerance. They are
also designed to support very high frequency signals.
Understanding the signal path for a global clock expands the understanding of the various
global clocking resources. The global clocking resources and network consist of the
following paths and components:
•
•
•

Clock Tree and Nets - GCLK

7 series FPGAs clock trees are designed for low-skew and low-power operation. Any
unused branch is disconnected. The clock trees can also be used to drive logic resources
such as reset or clock enable. This is mostly used for high fanout/load nets.
www.BDTIC.com/XILINX
7 Series FPGAs Clocking Resources User Guide
UG472 (v1.5) July 13, 2012
GTX Quad
116
GTX Quad
115
Device
Center
Bank 34
PCIe
HP
Bank 33
HP
Bank 32
HP
Clock Tree and Nets - GCLK
Clock Regions
Global Clock Buffers
www.xilinx.com
Global Clocking Resources
XC7K325T
Bank 18
HR
Bank 17
HR
Bank 16
HR
Top BUFGs
Bottom BUFGs
Bank 15
PCIe
HR
Bank 14
HR
Bank 13
HR
Bank 12
HR
GTX Quad
118
GTX Quad
117
GTX Quad
116
Device
Center
GTX Quad
115
Bank 34
HP
Bank 33
HP
Bank 32
HP
UG472_c1_29_010612
33