Bufr Use Models; Regional Clock Nets - Xilinx 7 Series User Manual

Chapter 2: Clock Routing Resources
•
Note:
after the clock returns.

BUFR Use Models

BUFRs are ideal for source-synchronous applications requiring clock domain crossing or
serial-to-parallel conversion. Unlike BUFIOs, BUFRs are capable of clocking logic
resources in the FPGAs other than the IOBs.
X-Ref Target - Figure 2-23
Clock Capable I/O
Clock Capable I/O

Regional Clock Nets

In addition to global clock trees and nets, 7 series devices contain regional clock trees and
nets. The regional clock trees are also designed for low-skew and low-power operation.
Unused branches are disconnected. The regional clock trees also manage the load/fanout
when all the logic resources are used.
Regional clock nets do not propagate throughout the whole 7 series device. Instead, they
are limited to only one clock region. One clock region contains four independent regional
clock nets. To access regional clock nets, BUFRs must be instantiated. For multi-region
support, see
www.BDTIC.com/XILINX
52
At time T after clock event 4, O begins toggling again at the divided by three
BRCKO_O
rate of I.
For proper operation, if the clock to the BUFR is stopped, then a reset (CLR) must be applied
I/O
I/O
I/O
I/O
I/O
P
I/O
N
I/O
P
I/O
N
BUFIO
BUFR
Figure 2-23: BUFR Driving Various Logic Resources
Multi-Region Clock
www.xilinx.com
Figure 2-23 is a BUFR design example.
CLBs
CLBs
Block
RAM
CLBs
CLBs
CLBs
CLBs
Block
RAM
CLBs
CLBs
Buffer—BUFMR/BUFMRCE.
7 Series FPGAs Clocking Resources User Guide
DSP
Tile
DSP
Tile
To more
FPGA logic
resources
ug472_c1_23_032111
UG472 (v1.5) July 13, 2012