Xilinx 7 Series User Manual page 23

Table 1-1: Summary of Clock Connectivity (Cont'd)
Clocking Function or Pin
BUFR
BUFMR
BUFG
BUFH
GT Transceiver Clocks:
RXUSRCLK
RXUSRCLK2
TXUSRCLK
TXUSRCLK2
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7 Series FPGAs Clocking Resources User Guide
UG472 (v1.5) July 13, 2012
Directly Driven By
Within the same clock region, BUFRs
are driven by:
• MRCC
• SRCC
• MMCM.CLKOUT0-
MMCM.CLKOUT3
• CLKFBOUT
• BUFMR from the clock region
above and below
• General interconnect
Within the same clock region,
BUFMRs are driven by:
• MRCCs (dedicated 1:1)
• GT clock outputs listed in this
table (see GT Transceiver
Within the same top/bottom half,
BUFGs are driven by:
• SRCCs
• MRCCs
• CMTs
• GT clock outputs listed in this
table (see GT Transceiver
• BUFRs (not recommended)
• Interconnect
(not recommended)
• Adjacent BUFG in the same top/
bottom half
Within the same clock region and the
horizontally adjacent clock region,
BUFHs are driven by:
• SRCC
• MRCC
• CMT
• BUFG
• GT clock outputs listed in this
table (see GT Transceiver
• Interconnect
(not recommended)
• Any BUFG
Within the same clock region, GTs are
driven by:
• BUFH
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Summary of Clock Connectivity
Used to Directly Drive
When used within the same clock region, BUFRs
drive:
• CMT
• Any clocking point in the same clock region
the BUFG can drive
When used within the same half top/bottom,
BUFRs drive:
• 16 BUFGs (not recommended)
When used within the same clock region and the
clock regions above and below, BUFMRs drive:
• BUFIOs
• BUFRs
Clocks:)
• CMT
• GT clock outputs listed in this table
(see GT Transceiver
• Adjacent BUFGs in same top/bottom half
• Any clocking point in the fabric and I/O
• CLB control signals
Clocks:)
• BUFH
When used within the same clock region, BUFHs
drive:
• CMT
• GT clock outputs listed in this table
(see GT Transceiver
• Any clocking point in the same clock region
the BUFG can drive
Clocks:)
N/A
Clocks:)
Clocks:)
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