Xilinx 7 Series User Manual page 31

Table 2-1: Clock-Capable Input Placement Rules (Cont'd)
Clock Inputs To
I/Os and/or sequential elements
(5)
using CMTs
I/Os and/or sequential elements
in a single clock region using
BUFR
I/Os and/or sequential elements
in up to three adjacent clock
(6)
regions
Only high-performance SelectIO
interfaces in one clock region
(50 I/Os)
www.BDTIC.com/XILINX
7 Series FPGAs Clocking Resources User Guide
UG472 (v1.5) July 13, 2012
Resource Utilization and Placement Rules
Throughout the device:
Clock-capable input > CMT > BUFG > global clock tree
In a single clock region or adjacent clock regions:
Clock-capable input > CMT > BUFR/BUFH > regional clock
tree/horizontal clock line
Input routing from CC inputs to CMT:
• A CMT must be placed in the same clock region as the
clock-capable input.
• CMTs can also be placed in the clock region immediately
above or below when multiple CMTs are needed.
• There is one CMT per clock region.
Clock-capable input > BUFR > regional clock tree:
• The clock-capable input must be placed in the same clock
region as the BUFR, I/Os, and sequentially clocked
elements.
• A specific clock-capable pin pair connects to a specific BUFR
and BUFIO. Therefore it is not recommended to manually
LOC the BUFR/BUFIO.
• There are four clock-capable inputs and four BUFRs per
clock region.
Clock-capable input > BUFMR > BUFR > regional clock tree
• I/Os and other sequential elements that the BUFRs are
driving must be in the same clock region or in the clock
region immediately above or below the clock-capable input.
The BUFMR must be used to drive BUFRs in the same clock
region and adjacent clock regions.
• A specific clock-capable pin pair connects to a specific BUFR
and BUFIO. Therefore it is not recommended to manually
LOC the BUFR/BUFIO.
• There are four clock-capable inputs, four BUFRs, and two
BUFMRs per clock region.
Clock-capable input> BUFIO > I/O clock tree
• The clock-capable input must be placed in same clock
region as the BUFIO and I/O flip-flops it will be driving.
• A specific clock-capable pin pair connects to a specific BUFR
and BUFIO. Therefore it is not recommended to manually
LOC the BUFR/BUFIO.
• There are four clock-capable inputs and four BUFIOs per
clock region.
www.xilinx.com
Clock-Capable Inputs
Valid
(1) (2) (3)
Clock-Capable
Input Pin
SRCC or MRCC
SRCC or MRCC
MRCC only
SRCC or MRCC
31