Xilinx 7 Series User Manual page 16

Chapter 1: Clocking Overview
X-Ref Target - Figure 1-3
Clock
Backbone
12
Interconnect
CE
12
BUFHs
Interconnect
CE
BUFGs
Figure 1-4
CMT/CC pin connectivity as well as the number of resources available in a region (a right
side region is shown here).
www.BDTIC.com/XILINX
16
To Bank
Above
CMT Backbone
32
CMT
PLL X0Yn in
Same Region
4
7
3
14
3
4
MMCM X0Yn
in Same Region
4
To Bank
Below
Figure 1-3: Single Clock Region (Right Side of the Device)
focuses on a more detailed diagram of the global BUFG and regional BUFH/
www.xilinx.com
2
I/O Bank
4
CE
CLR
2
4
4
Two BUFMRs
Four BUFRs
Four BUFIOs
7 Series FPGAs Clocking Resources User Guide
1
SRCC Pin Pair
1
MRCC Pin Pair
Clock
Region
HROW
50 CLBs
High
1
MRCC Pin Pair
1
SRCC Pin Pair
UG472_c1_32_020812
UG472 (v1.5) July 13, 2012