Mmcm Counter Cascading; Mmcm/Pll Programming; Determine The Input Frequency - Xilinx 7 Series User Manual

Chapter 3: Clock Management Tile
always be phase shifted regardless of frequency. When the end of the period is reached, the
phase shift simply wraps around round-robin style.
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X-Ref Target - Figure 3-7

MMCM Counter Cascading

The CLKOUT6 divider (counter) can be cascaded with the CLKOUT4 divider. This
provides a capability to have an output divider that is larger than 128. CLKOUT6 simply
feeds the input of the CLKOUT4 divider. There is a static phase offset between the output
of the cascaded divider and all other output dividers.

MMCM/PLL Programming

Programming of the MMCM/PLL must follow a set flow to ensure configuration that
guarantees stability and performance. This section describes how to program the MMCM/
PLL based on certain design requirements. A design can be implemented in two ways,
directly through the GUI interface (the Clocking Wizard) or implementing the MMCM/
PLL through instantiation. Regardless of the method selected, the following information is
necessary to program the MMCM/PLL:
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Determine the Input Frequency

The first step is to determine the input frequency. This allows all possible output
frequencies to be determined by using the minimum and maximum input frequencies to
define the D counter range, the VCO operating range to determine the M counter range,
and the output counter range. There can be a very large number of frequencies. When
using integer divides, in the worst case, there will be 106 x 64 x 136 = 868,363 possible
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PSCLK
PSEN
PSDONE
PSINCDEC
Figure 3-7: Phase-Shift Timing Diagram
Reference clock period
Output clock frequencies (up to seven maximum)
Output clock duty cycle (default is 50%)
Output clock phase shift in number of degrees relative to the original 0 phase of the
clock.
Desired bandwidth of the MMCM/PLL (default is OPTIMIZED and the bandwidth is
chosen in software)
Compensation mode (automatically determined by the software)
Reference clock jitter in UI (i.e., a percentage of the reference clock period)
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UG472 (v1.5) July 13, 2012
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