Xilinx 7 Series User Manual page 111

X-Ref Target - Figure B-4
Clock
Backbone
CE
BUFH
Left Side
or
Clock
Connections
BUFG
CE
Figure B-4: Clock Region in Artix-7 XC7A200T and XC7A350T Devices with GTP Transceivers
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7 Series FPGAs Clocking Resources User Guide
UG472 (v1.5) July 13, 2012
GT Quad Fabric - Multiple Columns of CLB/Block RAM/DSP
CLB
GTP
RX/TXUSRCLKs
25 CLBs
RX/TXOUTCLKs
IBUFDS O/ODIV2
CLB
CLB
GTP
CLB
RX/TXUSRCLKs
CLB
RX/TXOUTCLKs
IBUFDS O/ODIV2
CLB
CLB
RX/TXUSRCLKs
RX/TXOUTCLKs
CLB
IBUFDS O/ODIV2
CLB
GTP
CLB
GTP
CLB
RX/TXUSRCLKs
RX/TXOUTCLKs
25 CLBs
IBUFDS O/ODIV2
CLB
and I/O Banks (Right Side)
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CLKA CLK
CLKB
5x36K
10x
Block RAMs/
DSP48
FIFOs
Slices
HROW
5x36K
10x
Block RAMs/
DSP48
FIFOs
Slices
I/O Bank
SelectIO Logic
SelectIO Logic
SelectIO Logic
25 SelectIO
Logic Resources
PLL
BUFR
SelectIO Logic
BUFIO/BUFR
Any I/O Clock
BUFMR
Horizontal
Clocking Row
Any I/O Clock
BUFIO/BUFR
SelectIO Logic
BUFR
MMCM
25 SelectIO
Logic Resources
SelectIO Logic
SelectIO Logic
SelectIO Logic
UG472_aB_04_020812
BUFIO
CC
CC
BUFIO
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