Clock Alignment Across Clock Regions; Single Buffer Per Clock Region; Driving Multiple Bufios - Xilinx 7 Series User Manual

Appendix A: Multi-Region Clocking
For illustration purposes, the following clocking schemes use an MRCC as the input;
however, a GT clock can be used instead. Also, some of these examples show the topology
when using the built-in divide feature of the BUFR. The BUFR can divide by 1-to-8 in
integer steps. The divide value is specified by the BUFR_DIVIDE attribute during design.
Additionally, the BUFR has a BYPASS setting which turns off the divide capability and
disables the output clock enable (CE) and asynchronous clear for the divide logic (CLR).
For more information on BUFRs, see

Clock Alignment Across Clock Regions

Although the behavior of the BUFR primitive when using the BUFR_DIVIDE=BYPASS or
BUFR_DIVIDE=1 attributes is similar, the delay through the BUFRs when using
BUFR_DIVIDE=BYPASS is less than when using BUFR_DIVIDE=1. However, the delay
through a BUFR is the same when using the BUFR_DIVIDE=1 attribute or
BUFR_DIVIDE=2, 3...8. Therefore, when using BUFRs with the divide feature, the
non-dividing BUFRs should have BUFR_DIVIDE set to 1 rather than to BYPASS to ensure
the best possible clock alignment across the clock regions.

Single Buffer per Clock Region

Driving Multiple BUFIOs

When driving only I/O logic across three clock regions, the BUFMR can drive three
BUFIOs. Although BUFRs can perform this function, BUFIOs supply the highest
performance operation and drive dedicated clock nets within the I/O column. Group the
I/O logic by the three BUFIOs into three separate subsets, each is clocked by its own
BUFIO
X-Ref Target - Figure A-4
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102
(Figure A-4).
Clock Region Boundary
MRCC
Clock Region Boundary
Figure A-4: Driving Multiple BUFIOs
www.xilinx.com
BUFR Primitive in Chapter
BUFIO
BUFMR BUFIO
BUFIO
7 Series FPGAs Clocking Resources User Guide
2.
I/O Logic
I/O Logic
I/O Logic
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UG472 (v1.5) July 13, 2012