Detailed Vco And Output Counter Waveforms - Xilinx 7 Series User Manual

Chapter 3: Clock Management Tile

Detailed VCO and Output Counter Waveforms

Figure 3-9
VCO phase is shown with the appropriate start-up sequence. The phase relationship and
start-up sequence are guaranteed to insure the correct phase is maintained. This means the
rising edge of the 0° phase will happen before the rising edge of the 45° phase. The O0
counter is programmed to do a simple divide by two with the 0° phase tap as the reference
clock. The O1 counter is programmed to do a simple divide by two but uses the 180° phase
tap from the VCO. This counter setting could be used to generate a clock for a DDR
interface where the reference clock is edge aligned to the data transition. The O2 counter is
programmed to do a divide by three. The O3 output has the same programming as the O2
output except the phase is set for a one cycle delay. Phase shifts greater than one VCO
period are possible.
If the MMCM/PLL is configured to provide a certain phase relationship and the input
frequency is changed, then this phase relationship is also changed since the VCO
frequency changes and therefore the absolute shift in picoseconds will change. This aspect
must be considered when designing with the MMCM/PLL. When an important aspect of
the design is to maintain a certain phase relationship amongst various clock outputs, (e.g.,
CLK and CLK90) then this relationship will be maintained regardless of the input
frequency.
X-Ref Target - Figure 3-9
8 Phases
All "O" counters can be equivalent, anything O0 can do, O1 can do. In 7 series devices, the
O0 counter has the additional capability to be used in fractional divide mode. The
MMCM/PLL outputs are flexible when connecting to the global clock network since they
are identical. In most cases, this level of detail is imperceptible to the designer as the
software and Clocking Wizard determines the proper settings through the MMCM/PLL
attributes and Wizard inputs.
www.BDTIC.com/XILINX
86
shows the eight VCO phase outputs and four different counter outputs. Each
0°
45°
90°
135°
VCO
180°
225°
270°
315°
O0
O1
Counter
Outputs
O2
O3
One Cycle Delay
Figure 3-9: Selecting VCO Phases
www.xilinx.com 7 Series FPGAs Clocking Resources User Guide
UG472 (v1.5) July 13, 2012
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