Stacked Silicon Interconnect Clocking - Xilinx 7 Series User Manual

Stacked Silicon Interconnect Clocking

The clocking structure in the Virtex-7 FPGAs that are built using the stacked silicon
interconnect (SSI) technology is largely the same as the clocking structure in other,
monolithic 7 series devices (see
buffers (BUFGs) and 32 global clock lines (the clock backbone) in each super logic region
(SLR) which connect to adjacent SLR clock backbones via fast, dedicated, 3-stateable
vertical routes in the interposer. The interposer clock backbone is an extension of the clock
backbone used to connect the clock backbone for each of the SLRs. The ability for the 32
global clock lines to travel across the interposer means that the global clock lines run the
height of the device, enabling BUFGs in one SLR to clock components anywhere in the
FPGA. The interposer clock backbone is the only dedicated clocking resource across SLRs.
A BUFG on any SLR can drive a specific, dedicated global clock track on any or all other
SLRs. Each SSI SLR has 32 global clocks (BUFGs) available and other clocking resources are
the same as monolithic devices. However, only a total of 32 BUFGs can be used per FPGA.
The 32 BUFGs used can be any of the total available BUFGs in the SSI device with the
limitations described in the placement section. The BUFGs are only driven by the sources
within the SLR where they reside. Each SLR is three clock regions tall. Clocks that cross
from one SLR to an adjacent SLR are subject to more skew than clocks that stay within a
single SLR. Attention must be paid to minimize skew when placing clocking networks by
placing related BUFG clocking structures into the same SLR, which might require
duplication of external clocks.
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7 Series FPGAs Clocking Resources User Guide
UG472 (v1.5) July 13, 2012
Stacked Silicon Interconnect Clocking
Figure 2-28 and Figure
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2-29). There are 32 global clock
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