Xilinx 7 Series User Manual page 63

reference voltage to the VCO. The PFD produces an up or down signal to the charge pump
and loop filter to determine whether the VCO should operate at a higher or lower
frequency. When VCO operates at too high of a frequency, the PFD activates a down signal,
causing the control voltage to be reduced decreasing the VCO operating frequency. When
the VCO operates at too low of a frequency, an up signal will increase voltage. The VCO
produces eight output phases and one variable phase for fine-phase shifting. Each output
phase can be selected as the reference clock to the output counters
Figure
A special counter, M, is also provided. This counter controls the feedback clock of the
MMCM and PLL, allowing a wide range of frequency synthesis.
In addition to integer divide output counters, MMCMs add a fractional counter for
CLKOUT0 and CLKFBOUT.
X-Ref Target - Figure 3-2
Clock
General
Switch
Routing
Circuit
CLKIN1
D
CLKIN2
CLKFB
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7 Series FPGAs Clocking Resources User Guide
UG472 (v1.5) July 13, 2012
3-3). Each counter can be independently programmed for a given customer design.
Lock Detect
Lock Monitor
PFD CP LF
Figure 3-2: Detailed MMCM Block Diagram
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Lock
8-phase taps + 1 variable phase tap
9
VCO
Fractional Divide
(Fractional Divide)
Introduction
(Figure 3-2 and
O0
CLKOUT0
CLKOUT0B
CLKOUT1
O1
CLKOUT1B
CLKOUT2
O2
CLKOUT2B
CLKOUT3
O3
CLKOUT3B
CLKOUT4
O4
CLKOUT5
O5
CLKOUT6
O6
M
CLKFBOUT
CLKFBOUTB
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