Horizontal Clock Buffer-Bufh, Bufhce - Xilinx 7 Series User Manual

Horizontal Clock Buffer—BUFH, BUFHCE
The horizontal clock buffer (BUFH) drives a horizontal global clock tree spine in a single
region
pin (CE) that allows the clocks to be turned-off dynamically. BUFHs can be driven by:
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•
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•
X-Ref Target - Figure 2-26
Table 2-11: BUFH and BUFHCE Port List and Definitions
Table 2-12: BUFH and BUFHCE Attributes
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7 Series FPGAs Clocking Resources User Guide
UG472 (v1.5) July 13, 2012
(Figure 2-26). Each region has 12 BUFHs available. Every BUFH has a clock enable
MMCM outputs in the same region
BUFG outputs
GT output clocks in the same or vertically adjacent clock region
Local interconnect
Clock-capable inputs from either the left or right side I/O banks in the same vertically
adjacent regions/banks
Figure 2-26: BUFH and BUFHCE Primitives
Port Name Type
O Output
CE Input
I Input
Attribute Name
INIT_OUT Initializes the BUFH output to the specified value
after configuration. Sets the positive or negative edge
behavior. Sets the output level when changing clock
selection.
CE_TYPE Set to SYNC for CE to be synchronous from input to
output O, or set to ASYNC for asynchronous input to
output.
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BUFH
I
BUFHCE
I
CE
ug472_c1_24_061310
Width
1 Clock output port
1 Output clock enable port
1 Clock input port
Description
Regional Clocking Resources
O
O
Definition
Possible Values
0 (default), 1
SYNC (default),
ASYNC
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