Xilinx 7 Series User Manual page 15

X-Ref Target - Figure 1-2
Figure 1-3
of the device.
www.BDTIC.com/XILINX
7 Series FPGAs Clocking Resources User Guide
UG472 (v1.5) July 13, 2012
Clock
Backbone
Fabric
HROW
BUFG
BUFH
Figure 1-2: Basic View of Clock Region
shows a more detailed view of clocking in a single clock region on the right edge
www.xilinx.com
Clocking Architecture Overview
I/O
PLL
Bank
CC
CMT
BUFIO
Column
BUFMR
BUFR
CC
MMCM
CMT
Backbone
Fabric
GT
Quad
UG472_c1_31_020712
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