Xilinx 7 Series User Manual page 46

Chapter 2: Clock Routing Resources
BUFGMUX_CTRL with a Clock Enable
A BUFGMUX_CTRL with a clock enable BUFGCTRL configuration allows the user to
choose between the incoming clock inputs. If needed, the clock enable is used to disable
the output.
shows the timing diagram.
X-Ref Target - Figure 2-17
X-Ref Target - Figure 2-18
1
I0
I1
S
CE
T
BCCKO_O
O
at I0
In
•
•
•
•
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46
Figure 2-17 illustrates the BUFGCTRL usage design example and
BUFGMUX_CTRL+CE
Design Example
I1
I0
S
CE
Figure 2-17: BUFGMUX_CTRL with a CE and BUFGCTRL
2
T
BCCKO_O
Begin I1
Figure 2-18: BUFGMUX_CTRL with a CE Timing Diagram
Figure 2-18:
At time event 1, output O uses input I0.
Before time event 2, S is asserted High.
At time T , after time event 2, output O uses input I1. This occurs after a High
BCCKO_O
to Low transition of I0 followed by a High to Low transition of I1 is completed.
At time T , before time event 3, CE is asserted Low. To avoid any output clock
BCCCK_CE
glitches, the clock output is switched Low and kept at Low until after a High to Low
transition of I1 is completed.
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IGNORE1
GND
CE
CE1
S S1
I1
O
I0
S0
CE0
IGNORE0
GND
7 Series FPGAs Clocking Resources User Guide
Figure 2-18
O
ug472_c1_17_061310
3
T
BCCCK_CE
Clock Off
ug472_c1_18_033011
UG472 (v1.5) July 13, 2012