Xilinx 7 Series User Manual page 38

Fpgas clocking resources
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Chapter 2: Clock Routing Resources
X-Ref Target - Figure 2-4
I0
I1
CE0
CE1
S0
S1
IGNORE0
IGNORE1
O
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38
1
2
3
T
BCCCK_CE
T
T
BCCKO_O
BCCKO_O
at I0
Figure 2-4: BUFGCTRL Timing Diagram
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4
5
Begin I1
7 Series FPGAs Clocking Resources User Guide
6
T
BCCKO_O
Begin I0
UG472_c1_04_033030
UG472 (v1.5) July 13, 2012

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