Xilinx 7 Series User Manual page 94

Chapter 3: Clock Management Tile
modulation based on a given input frequency and SS_MOD_PERIOD. The restrictions
shown in
Table 3-9: Spread-Spectrum Generation Restrictions for MMCME2
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94
Table 3-9 apply when using spread-spectrum generation.
Parameter
F
MODULATION
Input Clock Frequency
SS_MODE(CENTER_HIGH)
SS_MODE (CENTER_LOW)
SS_MODE (DOWN_HIGH)
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Value
Minimum
Maximum
Minimum
Maximum
25 MHz < F < 35 MHz
IN
35 MHz < F < 50 MHz
IN
50 MHz < F < 75 MHz
IN
75 MHz < F < 100 MHz
IN
100 MHz < F < 150 MHz
IN
25 MHz < F < 35 MHz
IN
35 MHz < F < 50 MHz
IN
50 MHz < F < 75 MHz
IN
75 MHz < F < 100 MHz
IN
100 MHz < F < 150 MHz
IN
25 MHz < F < 35 MHz
IN
35 < F < 50 MHz
IN
50 MHz < F < 75 MHz
IN
75 MHz < F < 100 MHz
IN
100 MHz < F < 150 MHz
IN
7 Series FPGAs Clocking Resources User Guide
25 [kHz]
250 [kHz]
25 [MHz]
150 [MHz]
M = 28
D = 1
M = 21, 22
D = 1
M = 28
D = 2
M = 21, 22
D = 2
M = 21, 22
D = 3
M = 56
D = 2
M = 42, 44
D = 2
M = 56
D = 4
M = 42, 44
D = 4
M = 42, 44
D = 6
M = 28
D = 1
M = 21, 22
D = 1
M = 28
D = 2
M = 21, 22
D = 2
M = 21, 22
D = 3
UG472 (v1.5) July 13, 2012