Additional Use Models - Xilinx 7 Series User Manual

Chapter 2: Clock Routing Resources
BUFGMUX_CTRL uses the S pins as select pins. S can switch anytime without causing a
glitch. The Setup/Hold time on S is for determining whether the output will pass an extra
pulse of the previously selected clock before switching to the new clock. If S changes as
shown in
to Low, then the output will not pass an extra pulse of I0. If S changes following the hold
time for S, then the output will pass an extra pulse. If S violates the Setup/Hold
requirements, the output might pass the extra pulse, but it will not glitch. In any case, the
output will change to the new clock within three clock cycles of the slower clock.
The Setup/Hold requirements for S0 and S1 are with respect to the falling clock edge, not
the rising edge as for CE0 and CE1.
Switching conditions for BUFGMUX_CTRL are the same as the S pin of BUFGCTRL.
Figure 2-14
X-Ref Target - Figure 2-14
Other capabilities of the BUFGMUX_CTRL primitive are:
•
•

Additional Use Models

Asynchronous MUX Using BUFGCTRL
In some cases an application requires immediate switching between clock inputs or
bypassing the edge sensitivity of BUFGCTRL. An example is when one of the clock inputs
is no longer switching. If this happens, the clock output would not have the proper
switching conditions because the BUFGCTRL never detected a clock edge. This case uses
the asynchronous MUX.
design example.
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44
Figure 2-14, prior to the setup time T
illustrates the timing diagram for BUFGMUX_CTRL.
S
I 0
I1
O
Figure 2-14: BUFGMUX_CTRL Timing Diagram
Pre-selection of I0 and I1 input after configuration.
Initial output can be selected as High or Low after configuration.
Figure 2-15
Figure 2-16 shows the asynchronous MUX timing diagram.
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and before I0 transitions from High
BCCCK_S
T
BCCKO_O
illustrates an asynchronous MUX with BUFGCTRL
7 Series FPGAs Clocking Resources User Guide
T
BCCKO_O
ug472_c1_14_061310
UG472 (v1.5) July 13, 2012