Xilinx 7 Series User Manual page 110

Appendix B: Clocking Resources and Connectivity Variations per Clock Region
X-Ref Target - Figure B-3
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110
Clock
Backbone
CE
BUFH
or
Left Side Clock
Connections
BUFG
CE
Figure B-3: Clock Region in Kintex-7 and Artix-7 XC7A100T FPGAs with
GT Transceivers and no I/O Banks (Right Side)
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Fabric - Multiple Columns of CLB/Block RAM/DSP
CLB CLKA
CLKB
25 CLBs
CLB
5x36K
Block RAMs/
FIFOs
CLB
CLB
CLB
CLB
HROW
CLB
CLB
CLB
5x36K
CLB
Block RAMs/
FIFOs
CLB
25 CLBs
CLB
7 Series FPGAs Clocking Resources User Guide
GT Quad
CLK
GTX/GTH
RX/TXUSRCLKs
RX/TXOUTCLKs
IBUFDS O/ODIV2
10x
DSP48
Slices
GTX/GTH
RX/TXUSRCLKs
RX/TXOUTCLKs
IBUFDS O/ODIV2
GTX/GTH
RX/TXUSRCLKs
RX/TXOUTCLKs
IBUFDS O/ODIV2
10x
DSP48
GTX/GTH
Slices
RX/TXUSRCLKs
RX/TXOUTCLKs
IBUFDS O/ODIV2
UG472_aB_03_020812
UG472 (v1.5) July 13, 2012