Xilinx 7 Series User Manual page 54

Chapter 2: Clock Routing Resources
Table 2-10: BUFMR and BUFMRCE Attributes
To use BUFMR or BUFMRCE with BUFIOs, the interface pins must fit within three banks.
Similarly, if used with BUFRs, the logic must fit in up to three regions (if three BUFRs are
used).
X-Ref Target - Figure 2-25
The CE_TYPE attribute should always be set to SYNC to ensure that the clock output is
glitch free. If the clock output of the BUFMRCE is stopped (e.g., by deasserting CE), the
BUFR must be reset (CLR) after the BUFMRE is enabled again. The main purpose of CE on
the BUFMRCE is to provide a synchronous, phase-aligned clock to the BUFMR and
BUFIO. For more details on the use of BUFMR in driving BUFRs and BUFIOs, see
Appendix A, Multi-Region
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Attribute Name
INIT_OUT Initializes the BUFGCTRL output to the specified
value after configuration. Sets the positive or
negative edge behavior. Sets the output level when
changing clock selection.
CE_TYPE Set to SYNC for CE to be synchronous from input to
output O, or set to ASYNC for asynchronous input to
output.
Figure 2-25 shows the topology of the BUFMRCE.
BUFR
Region/Bank
BUFIO
Region/Bank
Region/Bank
Figure 2-25: Multi-Region Buffer Topology
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Description
CLR
CLR
BUFMRCE
CLR
Clocking.
7 Series FPGAs Clocking Resources User Guide
Possible Values
0 (default), 1
SYNC (default),
ASYNC
CE
MRCC
ug472_c1_25_030111
UG472 (v1.5) July 13, 2012