Xilinx 7 Series User Manual page 14

Chapter 1: Clocking Overview
X-Ref Target - Figure 1-1
Clock Region
Clock
Region
Horizontal
Center
Clock
Region
Clock
Region
CMT Column
CMT Backbone
I/O Column
Figure 1-1: 7 Series FPGA High-Level Clock Architecture View
A clock region always contains 50 CLBs per column, ten 36K block RAMs per column
(unless five 36K blocks are replaced by a PCI block), 20 DSP slices per column, and
12 BUFHs. A clock region contains, if applicable, one CMT (PLL/MMCM), one bank of
50 I/Os, one GT quad consisting of four GTs, and half a column for PCIe in a block RAM
column.
Figure 1-2
fundamental connectivity. The global clock buffer can drive into every region through the
HROW even if not physically located there. The horizontal clock buffers (BUFH) drive
through the HROW to every clocking point in the region. BUFGs and BUFHs share routing
tracks in the HROW. The I/O buffers (BUFIO) and regional clock buffers (BUFR) are
located inside the I/O banks. The BUFIO only drives I/O clocking resources while the
BUFR drives I/O resources and fabric resources. The BUFMR enables multi-region
chaining of BUFIOs and BUFR. The clock capable (CC) inputs connect external clocks to
clocking resources on the device. Certain resources can connect to regions above and
below through the CMT backbone.
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14
Clocking
Center
Horizontal Clock
Row (HROW)
BUFG 16
16
Horizontal Clock
Row (HROW)
Horizontal Clock
Row (HROW)
Clock Backbone
is a high-level overview of clock resources available in a clock region and their
www.xilinx.com
Clock Region
(HROW)
I/O Column
CMT Backbone
CMT Column
7 Series FPGAs Clocking Resources User Guide
UG472 (v1.5) July 13, 2012
Clock
Region
Detailed
View
GT Column
UG472_c1_30_020712