Chapter 2: Clock Routing Resources; Clock Buffer Selection Considerations - Xilinx 7 Series User Manual

Clock Routing Resources
7 series FPGAs have several clock routing resources to support various clocking schemes
and requirements, including high fanout, short propagation delay, and extremely low
skew. To best utilize the clock routing resources, the designer must understand how to get
user clocks from the PCB to the FPGA, decide which clock routing resources are optimal,
and then access those clock routing resources by utilizing the appropriate I/O and clock
buffers.
This chapter covers:
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Clock Buffer Selection Considerations

7 series FPGAs have a rich set of clocking resources. The various buffer types, clock input
pins, and clocking connectivity satisfy many different application requirements. Selecting
the proper clocking resources can improve routeability, performance, and general FPGA
resource utilization. For some applications and designs, floor planning or other types of
manual guidance can also greatly impact the implementation.
www.BDTIC.com/XILINX
7 Series FPGAs Clocking Resources User Guide
UG472 (v1.5) July 13, 2012
Clock Buffer Selection Considerations
Clock-Capable Inputs
Global Clocking Resources
Regional Clocking Resources
High-Performance Clocks
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Chapter 2
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