Clock Regions; Global Clock Buffers - Xilinx 7 Series User Manual

Chapter 2: Clock Routing Resources
In the 7 series FPGAs architecture, the pin access of the global clock lines are not limited to
the logic resources clock pins. The global clock lines can drive pins in the CLB other than
CLK pins (for example: the control pins SR and CE). Applications requiring a very fast
signal connection and large load/fanout benefit from this architecture.

Clock Regions

7 series devices improve the clocking distribution by the use of clock regions. Each clock
region can have up to 12 global clock domains. These 12 global clocks can be driven by any
combination of the 32 global clock buffers. The dimensions of a clock region are fixed to 50
CLBs tall (50 IOBs) and spanning the left or right side of the die. In 7 series devices, the
clock backbone splits the device into a left or right side. The backbone is not located in the
center of the die. By fixing the dimensions of the clock region, larger 7 series devices can
have more clock regions. The 7 series FPGAs supply from 8 to 24 clock regions.

Global Clock Buffers

There are 32 global clock buffers in every 7 series device. A CCIO input can directly
connect to any global clock buffer in the same half of the device. Each differential clock pin
pair can connect to either a differential or single-ended clock on the PCB. When used as a
differential clock input, the direct connection comes from the P-side of the differential
input pin pair. When used as a single-ended clock input, the P-side of the pin pair must be
used because a direct connection only exists on this pin. For pin naming conventions, refer
to the UG475: 7 Series FPGAs Packaging and Pinout Specification. If a single-ended clock is
connected to the P-side of a differential pin pair, then the N-side cannot be used as another
single-ended clock pin. However, it can be used as a user I/O.
CMTs in the top half of the device can only drive the BUFGs in the top half of the device
and CMTs in bottom half can only drive BUFGs in the bottom half. Similarly, only BUFGs
in the same half of the device can be used as feedback to the CMTs in the same half of the
device. Gigabit transceivers (GTs) can only directly connect to MMCMs/PLLs when the
CMT column extends into regions that also contain a full column of GTs and I/Os. The
Virtex-7T and Virtex-7XT devices have these full columns. The GTs and CMTs in the
Artix-7, Kintex-7, and Zynq-7000 families can only be connected using BUFHs (preferred)
or BUFGs.
Global clock buffers allow various clock/signal sources to access the global clock trees and
nets. The possible sources for input to the global clock buffers include:
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The 7 series FPGAs clock-capable inputs can drive global clock buffers indirectly through
the vertical clock network that exists in the clock backbone column. The 32 BUFGs are
organized into two groups of 16 BUFGs in the top and bottom of the device. Any resources
(e.g., GTX transceivers) connecting to the BUFGs directly have a top/bottom limitation.
For example, each MMCM in the top can only drive the 16 BUFGs residing in that top of
the device. Similarly, the MMCMs in the bottom drive the 16 BUFGs in the bottom.
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Clock-capable inputs
Clock Management Tile (CMT) consisting of mixed-mode clock managers (one
MMCM and one PLL per CMT) driving BUFGs in the same half of the device.
Adjacent global clock buffer outputs (BUFGs)
General interconnect
Regional clock buffers (BUFRs)
Gigabit transceivers
www.xilinx.com 7 Series FPGAs Clocking Resources User Guide
UG472 (v1.5) July 13, 2012