Xilinx 7 Series User Manual page 93

X-Ref Target - Figure 3-18
Another design trade-off is the decision to use a center spread or down spread. Selecting
SS_MODE (DOWN_HIGH, DOWN_LOW) spreads the frequencies to lower frequencies as
shown in
CENTER_LOW.
X-Ref Target - Figure 3-19
The decision to use down spread is often the result of considering the timing analysis
impact of spread spectrum. When using a spread-spectrum clock, the design must meet
timing at the highest frequency in the frequency deviation. Therefore, if a 100 MHz clock
with SS_MODE (CENTER_LOW) produces a 3% ( ±1.5%) center spread, the 100 MHz
clock with 3% center spread must pass timing analysis as a 101.5 MHz clock. However, if
SS_MODE (DOWN_HIGH) produces a 3% down spread, the input frequency is the
highest frequency within the frequency deviation. Consequently, for a 100 MHz clock with
3% down spread, the down-spread clock would continue to be analyzed by timing analysis
as a 100 MHz clock.
Because the average output frequency when using down spread is lower than the input
frequency, an asynchronous FIFO must be used for transferring data between the input
and output clock domains. Logic within the MMCME2 controls the spread-spectrum
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7 Series FPGAs Clocking Resources User Guide
UG472 (v1.5) July 13, 2012
F
IN
Figure 3-18: Center-Spread Modulation
(CENTER_LOW vs. CENTER_HIGH)
Figure 3-19. DOWN_HIGH will have similar frequency deviation to
F
IN
Figure 3-19: Down-Spread Modulation
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MMCM and PLL Use Models
CENTER_LOW
Time
DOWN_LOW
Time
CENTER_HIGH
UG472_c3_02_070212
DOWN_HIGH
UG472_c3_03_070212
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