Xilinx 7 Series User Manual page 82

Chapter 3: Clock Management Tile
Table 3-7: MMCM Attributes (Cont'd)
Attribute
COMPENSATION
SS_EN
SS_MODE
SS_MOD_PERIOD
Notes:
1. The COMPENSATION attribute values are documented for informational purpose only. The ISE® software tools automatically
select the appropriate compensation based on circuit topology. Do not manually select a compensation value, leave the attribute at
the default value.
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82
Type Allowed Values
(1)
String ZHOLD ,
EXTERNAL,
INTERNAL,
BUF_IN
Boolean FALSE, TRUE
String DOWN_LOW,
DOWN_HIGH,
CENTER_LOW,
CENTER_HIGH
Integer 4000–40000
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Default
ZHOLD Clock input compensation. Must
be set to ZHOLD. Defines how the
MMCM feedback is configured.
ZHOLD: Indicates the MMCM is
configured to provide a negative
hold time at the I/O registers.
EXTERNAL: Indicates a network
external to the FPGA is being
compensated.
INTERNAL: Indicates the MMCM
is using its own internal feedback
path so no delay is being
compensated.
BUF_IN: Indicates that the
configuration does not match with
the other compensation modes and
no delay will be compensated. This
is the case if a clock input is driven
by a BUFG/BUFH/BUFR or GTX/
GTH/GTP.
FALSE Enables spread spectrum
generation.
CENTER_HIGH Controls the spread spectrum
frequency deviation and the
spread type.
10000 Specifies the spread spectrum
modulation period (ns).
7 Series FPGAs Clocking Resources User Guide
Description
UG472 (v1.5) July 13, 2012