Bufr Alignment - Xilinx 7 Series User Manual

Appendix A: Multi-Region Clocking

BUFR Alignment

When using the built in divide capability of the BUFR (shown in
Figure
BUFRs, to align the BUFR divide counters across the multiple clock regions. This will
require using the BUFMRCE primitive, which allows the user to disable the output of the
BUFMR during the reset. To successfully align the BUFRs in adjacent regions, the
following procedure must be followed:
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•
•
•
To turn off clocks during circuit operations, that is after the reset/CLR signal to the BUFRs
is deasserted, disable the BUFMRCE using its CE pin. This ensures that the BUFRs
continue to be aligned when the clock signal is reinstated.
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A-7, the clock must be stopped at the BUFMR and reset signals applied to the
Connect the clock enable to the CE port of the BUFMRCE
Hold the CE pin of the BUFMRCE in its inactive state to disable the output of the
BUFMRCE
Reset all BUFRs by applying a reset signal to the CLR pin of the BUFR and releasing
the reset signal
Re-enable the BUFMRCE after the BUFR reset/CLR signal is released
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Figure A-6
7 Series FPGAs Clocking Resources User Guide
UG472 (v1.5) July 13, 2012
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